1. Field of the Invention
The present invention relates to a skew adjusting circuit, and more particularly to a skew adjusting circuit applicable to a high-speed data transmission system for adjusting delay difference between data transmission channels (inter-channel skew) on a data receiving side.
2. Description of Related Art
FIG. 16 is a block diagram showing a conventional skew adjusting circuit. In FIG. 16, the skew adjusting circuit 2000 comprises a transmitting-side printed-circuit board 2100 having a transmitting IC 2110 and wiring for transferring signals of the transmitting IC 2110, and a receiving-side printed-circuit board 2200 having a receiving IC 2210 and wiring for transferring signals of the receiving IC 2210. The transmitting IC 2110 includes a logic circuit 2111 and channel drivers Ch1-Chn, and the receiving IC 2210 includes channel receivers Ch1-Chn and a logic circuit 2211.
The skew circuit 2000 further comprises a transmitting-side connector 2120 for connecting wire of the transmitting-side printed-circuit board 2100, a receiving-side connector 2220 for connecting wire of the receiving-side printed-circuit board 2200, and a wire harness 2300 for interconnecting the transmitting-side connector 2120 and the receiving-side connector 2220.
When applying the skew adjusting circuit 2000 to a high-speed data transmission system, delay variations between channels can take place at the input of the receiving IC 2210 because of delay variations between channels of the transmitting IC 2110, delay variations between channels of the wire harness 2300, delay variations between channels of the connectors 2120 and 2220 and delay variations between channels due to wiring errors of the printed-circuit boards 2100 and 2200.
Thus, the conventional skew adjusting circuit 2000 can suffer from a malfunction (data error) when the inter-channel skew amounts to one bit.
To correct the variations at the receiving side, it must make fine adjustment of the skew on the printed-circuit board.
The adjustment has a problem of requiring an additional component for the adjustment, and being very difficult because of the extremely narrow bit width of the high-speed data transmission system.
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide a skew adjusting circuit capable of carrying out optimum correction of skew automatically by reading skew amounts, without setting particular skew amounts externally.
According to a first aspect of the present invention, there is provided a skew adjusting circuit comprising: a plurality of delay generating circuits, each of which is provided to one of channels, and includes a plurality of delay elements, each of the delay elements having a same delay amount; a plurality sets of flip-flops, each set of which is provided to one of the plurality of delay generating circuits except for a first delay generating circuit corresponding to a reference channel signal, the flip-flops of each set receive an output of a final delay element of the first delay generating circuit as a clock signal, and receive tap outputs of associated one of the plurality of delay generating circuits; a plurality of decoders, each of which receives outputs of the flip-flops of one of the plurality of sets of flip-flops; and a plurality of selectors, each of which receives an output of one of the plurality of decoders as a control signal, receives tap outputs of one of the plurality of delay generating circuits, and outputs a skew corrected signal.
The skew adjusting circuit may further comprise a plurality of latch circuits, each of which receives a skew mode signal as its clock signal, and an output of one of the plurality of decoders as its data input.
The skew adjusting circuit may further comprise a plurality of differential input circuits, each of which is provided to one of the channels, receives an external differential channel signal, and supplies its output to one of the plurality of delay generating circuits.
Each of the differential input circuits may comprise: a first first conductivity type MOS transistor having its source connected to a first fixed potential terminal; a first second conductivity type MOS transistor having its drain connected to a drain of the first first conductivity type MOS transistor, and its gate connected to a non-inverting input terminal of the differential input circuit; a second first conductivity type MOS transistor having its source connected to the first fixed potential terminal, its gate connected to the gate of the first first conductivity type MOS transistor, and its drain connected to its gate; a second second conductivity type MOS transistor having its drain connected to a drain of the second first conductivity type MOS transistor, and its gate connected to an inverting input terminal of the differential input circuit; a third second conductivity type MOS transistor having its source connected to a second fixed potential terminal, its drain connected to a source of the first second conductivity type MOS transistor and to a source of the second second conductivity type MOS transistor; a resistor having its first end connected to the first fixed potential terminal; and a fourth second conductivity type MOS transistor having its source connected to the second fixed potential terminal, its drain connected to a second end of the resistor, and its gate connected to its drain and to a gate of the third second conductivity type MOS transistor.
Each of the plurality of delay generating circuits may consist of a differential delay generating circuit that is supplied with an external differential channel signal, amplifies a difference voltage across its two input terminals, and outputs a voltage corresponding to the difference voltage.
Each of the differential delay generating circuit may comprise delay elements, each of which includes an operational amplifier.
Each of the differential delay generating circuit may comprise: a plurality of first resistors having their first ends connected to a first fixed potential terminal; a plurality of second resistors having their first ends connected to the first fixed potential terminal, each of the plurality of second resistors being paired with one of the plurality of first resistors; a plurality of first NMOS transistors, each of which has its drain connected a second end of one of the plurality of first resistors; a plurality of second NMOS transistors, each of which has its drain connected to a second end of one of the plurality of second resistors; a plurality of third NMOS transistors, each of which has its source connected to a second fixed potential terminal, and its drain connected to sources of the first and second NMOS transistors that are paired; a third resistor having its first end connected to the first fixed potential terminal; and a fourth NMOS transistor having its source connected to the second fixed potential terminal, its drain connected to a second end of the third resistor, and its gate connected to gates of the plurality of third NMOS transistors.
Each of the plurality of delay generating circuits may include a plurality of bias circuits for adjusting the delay amount of the delay elements.
Each of the plurality of delay generating circuits may comprise: a delay adjuster including a first resistor having its end connected to a first fixed potential terminal, a second resistor having its first end connected to a second end of the first resistor, and a third resistor having its first end connected to a second end of the second resistor and its second end connected to a second fixed potential terminal; a plurality of first conductivity type MOS transistors, each of which has its source connected to the first fixed potential terminal, and its gate connected to a connecting point of the first resistor and the second resistor; a plurality of bias circuits, each of which is connected to a drain of one of the plurality of first conductivity type MOS transistors; and a plurality of second conductivity type MOS transistors, each of which has its source connected to the second fixed potential terminal, its drain connected to one of the plurality of bias circuit, and its gate connected to a connecting point of the second resistor and the third resistor.
Each of the delay generating circuits may include an increasing number of delay elements and an increasing number of flip-flops corresponding to the delay elements.
According to a second aspect of the present invention, there is provided a skew adjusting circuit comprising: a plurality of delay generating circuits, each of which is provided to one of channels, and includes a plurality of delay elements, each of the delay elements having a same delay amount; at least one phase comparator that receives a reference channel signal and another channel signal; at least one first charge pump that receives an Up signal from the phase comparator; at least one first filter that receives an output of the first charge pump; at least one first ADC (analog-to-digital converter) that receives an output of the first filter as an analog input, and receives the reference channel signal as a clock signal; at least one first decoder that receives an output of the first ADC; at least one first latch circuit that receives a skew mode signal as a clock signal, and an output of the first decoder as a data input; at least one first selector that receives an output of the first latch circuit as a control signal, receives tap outputs of one of the plurality of delay generating circuits, and outputs a skew corrected signal of the reference channel signal; at least one second charge pump that receives a Down signal from the phase comparator; at least one second filter that receives an output of the second charge pump; at least one second ADC that receives an output of the second filter as an analog input, and receives the reference channel signal as a clock signal; at least one second decoder that receives an output of the second ADC; at least one second latch circuit that receives the skew mode signal as a clock signal, and an output of the second decoder as a data input; and at least one second selector that receives an output of the second latch circuit as a control signal, receives tap outputs of one of the plurality of delay generating circuits, and outputs a skew corrected signal of the channel signal.
Here, the skew adjusting circuit may further comprise a plurality of differential input circuits, each of which is provided to one of the channels, receives an external differential channel signal, and supplies its output to one of the plurality of delay generating circuits.
Each of the plurality of delay generating circuits may consist of a differential delay generating circuit that is supplied with an external differential channel signal, amplifies a difference voltage across its two input terminals, and outputs a voltage corresponding to the difference voltage.
Each of the differential delay generating circuits may comprise delay elements, each of which includes an operational amplifier.
Each of the plurality of delay generating circuits may include a plurality of bias circuits for adjusting the delay amount of the delay elements.
Each of the delay generating circuits may include an increasing number of delay elements and an increasing number of flip-flops corresponding to the delay elements.